TMS320VC33PGE150

TMS320VC33PGE150.pdf

Features of TMS320VC33

High performance floating point digital signal processor (DSP) :

TMS320VC33-150

Instruction cycle time of 13 nanoseconds

150 million floating point operations (MFLOPS) per second

75 million instructions per second (MIPS) 

TMS320VC33-120

Instruction cycle time of 17 nanoseconds

120 operations per second

60 MIPS

Dual access SRAM (SRAM)34K × 32bit (1.1-Mbit) on-chip word configuration of 2 × 16K plus 2 × 1k blocks for improved internal performance

X 5 PLL clock generator

Very Low Power: & Lt; 200mw@150mflops

32-bit high performance CPU

16-bit/32-bit integer and 32-bit/40-bit floating point operations

Four internal decoding pages are selected to simplify the interface between I/O and storage devices

The bootstrapper loader

EDGEMODE optional external interrupt

32-BIT instruction word, 24-bit address

Eight extended precision registers

On-chip memory mapping peripherals:

A serial port

Two 32-bit timers

Direct Memory Access (DMA-RRB- coprocessor for concurrInO i/o CPU CPU operations

The 0.18 μm (low-efficiency gate length) TIMELINETM technology from Texas Instruments (TI) was used

144 pin thin square flat package (LQFP)(PGE suffix) 

Two address generators with eight auxiliary registers and two auxiliary register arithmetic units (Arau) 

Two low power modes

Two and three operand instructions

Single-cycle parallel arithmetic/logic unit (Alu) and multiplier execution

Block repeatability

A zero-overhead cycle with a single-cycle branch

Conditional calls and returns

Interlock instructions supported by multiprocessing

Bus control register configuration gating control waiting state generation

1.8 V (kernel) and 3.3 V (I/O) supply voltages

IEEE standard 1149.1(JTAG) based on simulation logic for on-chip scanning

IEEE standard 1149.1-1990 standard test access port

Timeline is the trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

TMS320VC33 description

The TMS320VC33 DSP is a 32-bit floating-point processor manufactured in 0.18 μm four-stage Metal CMOS (TImeline) technology. TMS320VC33 is part of Texas Instruments' TMS320C3X-GENERATION DSP.

TMS320C3X's internal bus and special set of digital signal processing instructions have the speed and flexibility to perform up to 150 million floating point operations (MFLOPS) per second. TMS320VC33 optimizes speed by implementing in hardware what other processors do in software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

TMS320VC33 can perform parallel multiplication and ALU operations on integer or floating-point data in a single cycle. Each processor also has a general-purpose register file, a program cache, a dedicated Arau, internal dual-access memory, a DMA channel that supports concurrent I/O, and a shorter machine cycle time. High performance and ease of use are the result of these capabilities.

Large address space, multiprocessor interfaces, internally and externally generated wait states, one external interface port, two timers, one serial port, and multi-interrupt architecture greatly enhance general-purpose applications. TMS320C3X supports a variety of system applications, from host processors to dedicated coprocessors. High-level language support can be easily achieved through register-based architecture, large address space, powerful addressing mode, flexible instruction set, and well-supported floating-point algorithms.

TMS320VC33 is a superset of TMS320C31. Designers now have additional 1m-bit on-chip SRAM, maximum throughput of 150mflops, and multiple I/O enhancements that make it easy to upgrade to the current system or create a new baseline. This data sheet provides the information needed to take full advantage of the new capabilities of the TMS320VC33 device. For general TMS320C3X architecture and programming information, see the TMS320C3X User Guide (literature number SPRU031) .